[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [N8VEM-S100:993] Clock generator for S-100 80386 Board.
- To: email@example.com
- Subject: Re: [N8VEM-S100:993] Clock generator for S-100 80386 Board.
- From: "Pontus Oldberg" <pontus....@invector.se>
- Date: Fri, 20 Jul 2012 11:17:40 +0200
- Authentication-results: gmr-mx.google.com; spf=neutral (google.com: 22.214.171.124 is neither permitted nor denied by best guess record for domain of pontus....@invector.se) smtp.mail=pontus....@invector.se
- Importance: Normal
- In-reply-to: <firstname.lastname@example.org>
- References: <email@example.com>
- Reply-to: pontus....@invector.se
- User-agent: SquirrelMail/1.4.19
John Monahan skrev:
> I am currently laying out a schematic for our S-100 80386 board. I have a
> question perhaps somebody here could help on.
> I want to have it so the 80386 normally communicates over the S-100 bus
> I/O, INTA's and say a small block of static RAM (adjustable say ( 64K-
> at typical S-100 bus speeds (~8Mhz). For the rest of the memory address
> space the CPU would communicate with a daughter board completely
> of the S-100 bus (except for power at high 80386 speeds (20-33MHz).
> Clearly there is no way the S-100 bus could handle a 20 or 33MHz clock
> would be used with the daughter RAM board.
> What I had in mind was a duel clock frequency arrangement where the CPU
> would communicate over the S-100 bus at say 8-10MHz and switch to a higher
> speed for the daughter board (where it would be most of the time). I
> the process to be dynamic with a glitch free clock switch depending on the
> CPU address lines, and/or M/IO lines being used.
> I have been trying to think how best to do this. Current thinking would be
> that the CPU "normally" runs at the low speed. But if it finds itself
> accessing the daughter board flips into high speed mode. The issue is how
> best to do this? Both in terms of CPU cycle timing and clock phase.
> Because the Address & M/IO signals come out early in the cycle (at drop of
> ADS*), I could lengthen the clock pulse then. However I trying to figure
> out how to construct a 74Sxx circuit so I won't glitch the very fast CLK2
> signal changing it from say 33MHz to 33/4 or 33/8 MHz. picking a signal
> a divide by N counter (e.g. 74S107's). Has anybody seen a circuit that
> allows such an alternate frequency input that would be glitch free.
> I did come across a chip by VIA technologies called a VT8225 (see
> Looked like it could be used for this purpose. However searching the web I
> cannot find anybody that sells it in small quantities. It's also unclear
> the frequency can be changed "on the fly" or is to be set just with pin
> jumpers etc.
> An alternative approach would be to put many wait states on the S-100 bus
> when it is being accessed. However in this case the actual pWR*, pDBIN
> signals would be very narrow and not "stretched" and so probably missed by
> the S-100 boards even though the rest of the R/W cycle would be OK.
> Anybody got suggestions etc.
> John Monahan Ph.D
> e-mail: mon...@vitasoft.org
> Text: mon...@txt.att.net
I would recommend you build a 386 local bus <-> S-100 bridge. This bridge
would generate all S-100 signals with correct timing and relationship
while holding the 386 in wait state. This way you can run the S-100 bus at
max speed while slowing the processor down only while accessing the bus. I
guess a CPLD or a few PLD's and buffers (which you already need) would do