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RE: [N8VEM-S100:2957] 6502 v1 CPU board and the EPROM/RAM board (sINTA problem)

On the original V1-6502-non-IEEE 696 board which you have (and which BTW, I did not lay out),  it looks like sINTA (S-100 pin96)  is not connected to anything.  I assume because the original users assumed no interrupts, certainly the Intel 8259A style chips would not be compatible.    On the V2 board this and a number of other things were “fixed”.   


On the V1 the line will float high which is what you are seeing.  The ROM board assumes a IEEE-696 format and is counting on sINTA being low normally. 


Two fixes.

If you are not using INT’s just bend out and tie pin 5 of U1b low.   Not a great option for future boards. 


Better, would be to use  the spare 74LS05 (U42F) OC gate. Tie pin 11 high and pin 10 to S100 pin 96.

BTW, if you intend to do serious work with the 6502 try and get your hands on the V2 master/slave board






From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Fabio Battaglia
Sent: Thursday, March 27, 2014 3:06 PM
To: n8vem...@googlegroups.com
Subject: [N8VEM-S100:2957] 6502 v1 CPU board and the EPROM/RAM board (sINTA problem)


Hi everyone!
Today I received the last component needed to get my EPROM/RAM board V1 together. My plan is to use it as a RAM board for my 6502 v1 CPU card.
I brought the card together, configured the switches and... nothing. The card did not work, so I started investigating and found something very interesting:
I'll describe it referencing the schematics for the 6502 v1 board found here (http://s100computers.com/My%20System%20Pages/6502%20Board/Printing%20S100_6502-sch1.pdf) and for the EPROM board here (http://s100computers.com/My%20System%20Pages/PROM%20Board/Printing%20S100_EPROM-sch%20(V2%20Final).pdf).

The EPROM/RAM board decodes the IO_REQUEST signal ORring between sOUT, sINP and sINTA (see on the middle-left on the schematics). IO_REQUEST (when low) is then used to generate the CS* signals for the onboard ram/flash/whatever.
Much to my surprise, i noticed IO_REQUEST came out as always high! I traced the problem to U1B (a 74LS32) doing an OR between the output of U1A (made using sOUT e sINP, which pulses high and low correctly) and sINTA. sINTA is not generated by anything on my system (as you can see in the 6502 v1 schematics it is not connected) and the LS32 doesn't like this: the output of the OR operation is always true, which I think is wrong and causing the board not to work correctly

My first idea was to add a jumper on the proto-zone of the 6502 CPU card, giving the option to tie sINTA line to ground, but I'm afraid I might have misunderstood the purpose of the circuit and risk doing any damage (Yep, still a newbie :-) ). Any idea/opinion/advice?


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