Made a note on the bottom of this web page Gary.
http://s100computers.com/My%20System%20Pages/IDE%20Board/My%20IDE%20Card.htm
Thanks all for the detective work. If the is ever a V3 board we should include the change
John
From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of geka...@gmail.com
Sent: Monday, July 21, 2014 7:29 PM
To: n8vem...@googlegroups.com
Subject: [N8VEM-S100:4663] Re: CF IDE card checkout and final assembly problem
My system had previously been working fine with the Z80 CPU card and CP/M, but when adding an 8088 card the timing problem showed up.
A huge thanks to Dave and Thomas for this fix.
John - perhaps it's worth adding to the IDE board write-up, as I suspect other will run into the same issue down the line.
I did the modification on a small 14 pin header (I didn't want to modify the board until I was certain it would fix the problem). It worked nicely.
- Gary
On Tuesday, June 10, 2014 10:44:43 AM UTC-4, Thomas Owen wrote:
First of all, I want to thank everyone for their generous time and suggestions in resolving my Drive Selection problem. As John accurately points out, there is a wide variety of old equipment out there and sometimes you have to be prepared for the situations like this - mixing the old and the new.
That being said, however, is why I got the old IMSAI out of the closet after many years - I really miss the tangle of cords, probes, extender cards, and smell of smoke (that usually brings the wife into the room).
I look forward to building more of the 'new' boards - I already have the ZFDC and the Ram/Rom is on order. The CPU should be next but I with the IMSAI and the Front panel, well, I hate to give that up so quickly.
So, I may have to deal with more of these little quirks that arise from this chassis, front panel, and a 1977 CPU - and that is ok with me...
Shown below is what my drive select now looks like - Originally I looped the FF clock through unused gates just to get some delay, but then I took Dave's (yoda) idea and simply inverted the signal from U15 pin1 through a unused gate (U15 pins 4,5,6) and back to U16 pin 3. This places the RISING edge square in the middle of my data on DO0 and the Flip flop changes as it should. Is it perfect? Probably not, but it may work for others out there fighting similar timing issues.
Thanks again to all,
Thomas
Shown in the diagram is the Clock and Data inputs (pins 3 and 2) at the Flip Flop:
Data bit 0 (Drive A):
Data bit 1 (Drive B):
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