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Re: CF IDE card checkout and final assembly problem

OK - I went back and looked at your traces (they were confusing me because of the labels - but looked at the assignments you made).  It is clear in first example that the rising edge of U15_out is in the middle of DO0 being low which is good.  In the second trace on the rising edge of U15_out, DO0 is also rising - you are in no man's land definite race condition.  DO0 is too late in the cycle - I don't understand why it is late in that case but correct in Trace 1.  It looks like if U15_out had an inverter in line before the clock input then the circuit would work?  Aren't the S100 signals valid on falling edge not rising edge and the flip-flop is triggered on rising edge causing the race condition ?


On Monday, June 9, 2014 1:13:55 PM UTC-5, Thomas Owen wrote:

If I manually set pin 2 of the flip flop to either high or Low then the Drive Select works. 

pin 2 held high, console out DO34,01 changes to Drive B.

It appears to me that the FF is always clocking in a 0 due to timing on the input.

I have two different CPU's in a IMSAI chassis (with front panel).  CPU is a Cromemco ZPU and the other is the IMSAI 8080 - both exhibit same behavior.

DO0 definitely changes (see the earlier screen shots) for the different commands 'QO34,00' and 'QO34,01'.


On Sunday, June 8, 2014 7:58:45 PM UTC-4, Thomas Owen wrote:
I had posted this to the thread dealing with ordering this card, but decided to post a new topic dealing with the problem I have had with final checkout of the board.

During assembly the board passed all the 'in progress' checks.  The final steps were to output to different ports:

I have output the following and everything passes:

QO33,80 ; Configures ports A, B and C as output ports
QO32,2B ; Selects right hand pair of digits
QO30,01; display 01on right digit pair and work through each bit - all ok

QO32,2c; Selects middle pair of digits
QO30,01; Should display 01 on middle digit pair, work through each bit - all ok

QO32,2d; Selects left hand pair of digits
QO31,01; Should display 01 on left digit pair, work through each bit - all ok

All displays are correct.

Now the final step is the Drive Select and that is where I am having trouble:

Board always comes up with 'Drive A' selected

Now,  QO34,0; no change

Reset, start again:

QO34,1; no change

I can never select drive B.  

Several generous members (thank you David Fry) have made suggestions, and here is where I now stand:

My preliminary check this afternoon shows me that there is a timing issue at U15, the 74ls02.  Using my logic analyzer and monitoring the inputs and the output (which clocks the drive select flip flop) I see a big timing difference between SEL_SECOND and WR.

What this means is that the output of the gate never goes high allowing the bit change to effect drive change/selection.

I am going to get some screen shots from the analyzer tomorrow, and if anyone has any suggestions I would greatly appreciate it.