The whole thing is held together right now with wires jumpers and is a mess. Definitely will need another pair of prototype boards. Andrew will be busy!
Would this circuit (or a derivation) do the trick?
"The circuit shown below allows switching between two clock sources with no glitches, even when the two clocks are generated by separate, non-synchronised oscillators.
Clock A and Clock B are the two separate clock inputs
D0 is the processor D) data line
Reset is the processor reset signal
Write Port is created by gating together the address select signal, R/W and phase2. It should pulse low while phase 2 is high and the CPU is writing to the clock speed select circuit.
When the CPU changes the clock speed, the Write Port line goes low. At the end of the write cycle, the currently selected clock goes low, which loads the low Write Port signal into the two right-hand flip-flops. The lower flip-flop then holds the clock output to the CPU low via the lower of the 2 and gates.
After a delay of a few nanoseconds, determined by the propagation delay in the logic that creates the Write Port line, the Write Port line will go high, loading the left-hand flip-flop with the clock select signal. This then selects the desired clock signal via the 74HC157 multiplexer.
The clock pulses clock a high state into first the upper and then the lower of the two right-hand flip-flops. Until the second flip-flop goes high, the CPU clock line is held low. This generates a delay of between one and two cycles of the new clock, during which the CPU clock is held low.
Since the output of the flip-flop which gates the CPU clock changes when the clock line is already low, there are no switching glitches fed through to the CPU clock."On Tue, Feb 26, 2013 at 10:52 PM, John Monahan <mon...@vitasoft.org> wrote:
Hi Guys, I have a question for any experienced 74xxx era chip hardware guy out there. It’s a bit complicated, so bear with me as I explain..
I have a working 80386 S100 CPU board which with a CPU input clock (CLK2 as Intel calls it) of 20 MHz. The bus itself and all support chips run at half this speed (10 MHz), Intel’s terminology CLK.
Works fine and can access up to 16MG RAM on the S100 bus with our 4MG RAM boards.
Andrew and I are adding “Daughter boards”, initially static RAM but later DRAM to get capacity (hopefully) into the GB range. For this I am using an “over the top” set of ribbon cables with connectors to join one (or more) boards to the CPU board which has all the address lines, data lines and a few control lines. Currently this arrangement is working nicely with a 2MG static prototype board. All this was challenging but alas now seems to be fine. 32 Bit access is working great (as is pipelining if you know what that is).
Here is my problem. The CPU is accessing that Daughter board at 10MHz but should be capable of running at a the max speed of the CPU, for my chips 40MHz.
The obvious solution is to switch speeds (with 77LS682 address line logic) if a RAM access is above 16MG. Have that working fine too. But here is the problem, if I use a 2 line to one line output chip like a 74LS157 I glitch the clock more or less randomly.
Does anybody have a circuit where you can switch frequencies but guarantee that the instance of the switchover will not have one pulse (square wave) shorter that the shortest wave of the two frequencies. It probably does not matter if it’s longer but the CPU just does not seem able to take even one higher frequency pulse (because the switch took place between pulses). Hopefully I’m making myself clear. If not please let me know I will try and elaborate.
Any suggestions would be appreciated.