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Re: An updated (V3) version of our Dual IDE/CF card S100 bus board

Thanks for quick feedback guys!  Rather than clog the system up with separate reply e-mails I'll do them all here.


Frank's suggestion to using a 16V8 GAL for the U13 74LS154…  yes Frank I did consider that, but I'm really trying not to wander too far from the time proven design. It's presumably a timing insensitive part of the circuit (used only for the HEX display),  but I'm somewhat reluctant to add another GAL. Assuming a number of beginners in the future will want the board with the GAL, it doubles the programming/stocking effort.  74LS154's are really not that hard to find. Jameco for example stocks them (#46738). Granted they are big and ugly, but real estate is not a problem with this board.


David's point about the Hard Disk IDE connector being in upside-down is valid.  I’m not sure how it ended up that way. I think in the early days I was using an IDE cable where the ribbon folded backwards on the connector for strain relief.  Anyway, point well taken,  I’ll flip it around to be line the CF card connectors.


Mike I not quite sure what you had in mind for the …”ABCDEFGH instead of IJKLMNOP” issue.  Remember for CHS addressing we need the display to distinguish the Head register on the “High Cylinder" HEX display.  The board has a separate access for this display via U12 (74LS244).   We trick the display by first sending head information to the IDE drive via the 8255 port A in the normal way.  We then get the head information to the upper two HEX displays by sending the data to port B of the 8255 and pulsing the IDE High Cylinder line again.  The IDE drive ignores this data on its upper 8 bits data line but the HEX LED displays latch the data. (To illustrate the selected head better I actually put the 4 head bits in the displays high nibble).  See the web page for more detail under “Notes on CHS & LBA addressing”.


Gary, yes the idea of using the one GAL is to simplify and speed up the port addressing.  Those 74LS682’s look nice but the is a lot going on inside them. Overkill for what we need and somewhat slow.   That combined with switching to the 74LS00’s for the sector RD/WR signals I’m hoping will increase reliability at high speeds.


There is still some real estate available on the board. Any other diagnostic function you think we should add.







On Tuesday, February 10, 2015 at 11:13:58 AM UTC-8, monahanz wrote:

Guy's I thinking of doing another run of our now, old, S100 bus IDE/CF card board.  There are probably close to 150 of them out there by now.

It's described here:-


Hard to believe but the first board was back in 2010!


While the V2 board seems to work fine for most people, there may be some things "not quite right" with the design for high bus speeds around 10MHz and with fast CPU's like the 80386 and with multi-sector reads with MSDOS etc.


I decided the time was right to fine tune the board for another run, a V3 version.   There are a few things I wanted to do.


1.    I do not want to change the basic 8255 driven circuit and all the software I and others have over the years written for the board.  Sure if I were to do it all over again I would probably have done it different using perhaps a faster Zilog PIO or an onboard fast fully dedicated Z80 (as for our ZFDC board) or Propeller etc.     The NEC or OKI 82C55-2’s are dirt common and seem to be able to handle anything the CPU sends to them.


2.    I want to hand lay down broad power traces to all the boards IC’s for more even power distribution – particularly to the power hungry HEX displays.


3.    I have inserted a trace “Keep out Area” on the front of the board so there is no danger of the IDE adaptors touching a critical trace.


4.    I added a single TO-3 V regulator (e.g. 78H05’S) capable of delivering high currents without overheating the board locally. Yes I know we should be going to the switching regulators, but this is often a first board for builders, wanted to keep it simple.


5.    However I did bend the rules a little and add one 22V10 GAL.  This greatly simplifies the board and really speeds up the port addressing and the potential drive select/reset issues some were having.  I realize not everybody is familiar with GAL’s. For those people and beginners I will supply the pre-programmed Lattice 22V10 GAL.  Will of course supply the PALASM code for others. Again these GAL’s are fairly common (Jameco #39159 for the 15ns variety).


6.    I have switched over to using a 74LS00 (instead of the OC 7403’s) for the critical RD/WD circuit.  This is based on (Roger & others) observations.  Still a bit worried about this, but it’s a prototype can easily add pull-ups and a 7403.


7.   People should be able to simply switch IC’s from the old board to this new one. Only a new GAL IC is required.


8.   Last but least I relabeled much of the Silk Screen to be more relevant. For example placing IC numbers above their pin locations. 


I’m attaching a suggested schematic and a picture of the proposed V3 board.  Could people take a look at it? Any suggestions etc. will be gratefully received. Dave in particular I would really appreciate your input. You have a keen eye for detecting potential issues and know this board well.  I have added my complete working KiCAD file folder at the very bottom of the page of the above URL for anybody that has the time to look.