I have corrected the web page David. Please keep track of other things as you go along. I’m a bit frustrated here because when you get to the finishing line you will find the board does not read/write S100 RAM, but does the onboard RAM. Fortunately the 68K monitor works fine. I have little time here for the next few days – not helping the overall frustration John John Monahan Ph.D e-mail: mon...@vitasoft.org Text: mon...@txt.att.net From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of yoda I finished up the DTACK and WAIT The only thing I see not mentioned is that the XFERII LED now lights all the time - (I think by K2 1-3 and K6 1-2 - looks like it will permanently stay on ?)
Hi John Another quick one - when do you insert pin 9 of U31 back in place as that is temporary - I don't see mention of that. Hi John Been working through your notes and found a couple errors I think. I have free running working great I am working through the DTACK and WAIT state circuit - 3rd paragraph where you are looking at signals on U40 (BTW I only have 74ls367 and it seems to work so far) I think you mean 7 is high and 9,11 and 13 will pules (not 79) but for this to happen I think you need to have U42 in plugged in as well. You do have it plugged in on your picture but don't mention to add it. If you don't then pin 7 will pulse. Further down though I am not there you on the Watchdog time in first paragraph you say insert JP9 that should be J9 instead. I am probably going to call it a night soon but it looks like things are working so far. Dave
Hi John - read through what you have updated so far looks good and I will be starting now. BTW you probably should update your web site to say V3 instead of V2 as on Andrew's site it is referred to as V3 and technically it is the third version if you count the Wilcox board as V1. Dave John. Thanks for the explanations - they make sense. Might want to publish what you have - more eyes could be helpful. I am ready to start populating - want to do some voltage checks, and clock - then will start populating enough to do the NOP tests - then I next plan to do the Character out loop with no memory to get that working then populate the memory and use the memory checking code that does not use a stack (all inline code) to make sure the on board ram is working then start branching out to check off board memory. I assume those are similar to the steps you have done. Dave Dave I am in the middle of bringing my board up. I have so far step by step assembly notes for everybody with tests at each step. I am bringing it up as a bus master first. Have monitor and onboard RAM working fine but for some reason all bus RAM is showing up as FF’s. Currently debugging! There are a lot of jumpers each of which will require a detailed explanation. I’m am trying to get it debugged/ written up before others start into it so excuse the quick reply. All the K’s have to do with master/slave switching. For a simple master, XFERI & XFERII just go to ground, K4 2-3 (slight bug, to have 68K LED active bend out pin 1 of U71 and wire wrap 1,2 & 3 together). JP13 is a carryover from the original Wilcox board and is basically now just a connection point in case one wants to hookup a external single step circuit as he had originally. Yes always closed. See below for others John From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of yoda Hi John I have some questions on the jumpers. I am not quite sure what the settings should be for K1, K2, and K4 as they are new and probably have something to do with the TMA stuff. Also it seems that JP13 must always be Closed or I don't understand the function of it. Here is what I have come up with so far - I am going to start using as a bus master with no SMB currently in the system I have labeled some with ? Could you clarify or confirm them? Thanks Dave J9 Open Watch Dog Timer ------- Closed J10 Closed Auto Vector enabled J13 Open Enable Various Interrupts J14 1-3, 2-4 ROM at XX8000 J15 Closed Enable Boot Feature JB1 1-2, 3-4 Values for 28C256 eeprom JB2 3-4, 7-8 Values for 62256 memory JP1 Open OV_A JP2 Open OV_B JP3 Open OV_C Do not add this circuit until later, it’s for DMA in slave mode will explain later. JP4 1-2 Connect to SDSB* JP5 Open S100 pin 65 Only if these signals are not generated by front panel or our SMB JP6 1-2 Bus_RESET* JP7 1-2 HOLD* JP8 1-2 SLAVE_CLR* JP9 1-2 POC* JP10 1-2 BUS_RESET* JP11 1-2 MWRT* JP12 1-2 Clock* JP13 1-2 ???? seems this needs to be always connected see above Do not add this circuit until later it’s for DMA in slave mode will explain later. JP14 Open BR* ??????? JP15 1-2 PHLDA* JP16 Open S100 pin 66 These are fine K1 1-3 XFERI ????? K2 3-4 XFERII ????? K3 1-2 NMI* K4 2-3 XFERII K5 2-3 DODSB* K6 2-3 HALT K7 2-3 bA20 ------- 1-2 P2 dependent Sets number of Wait States The whole U2,U3 cascade is for handshaking on master to slave transition and DMA designation In master mode this whole circuit can be ignored P5 1-2 TMAXPU* ????? P6 1-2, 5-6 Passes Master Reset through ???? For master P6 1-3 and 5-6 check pins carefully -- -- |