That’s a good point Dave, S-100 Port I/O is solid (at least ports 0 and 1). It has all the symptoms of something on the edge timing wise. I do have the original V1 board and that did work fine. Unfortunately it was hacked up a bit and I removed everything from it way back. In retrospect I should have held on to it. Could always rebuild! I will try logic analyzer as well. BTW the monitor has a command to read or write to S100 RAM in a loop just for this purpose. John From: yoda [mailto:yo...@r2d2.org] Hi John I don't think it is address latching - if you look at the V1 schematics they are not latched either and I am able to run the V1 board with 8MHz cpu clock - if you are using the 6 MHz oscillator you are only running at 3 MHz so I have a feeling something else is causing the problem (I am running with a 2MHz oscillator which is a 1MHz cpu clock just to eliminate timing problems. I plan to put a logic analyzer on the bus and look at the control signals first. Just speculating, since you can do I/O the address lines and data are probably ok sounds like it might be some of the memory control signals that might not be showing up with the right timing. I know Pontus found some problems with the S100 state machine and had to substitute in some 74F logic for memory to work - I don't know if you have those on this board - I have them in the V1 board - I don't know if they are incorporated on this though I notice a couple chips are denoted as 74F on the board. Hopefully we will know more by the end of tomorrow - I am sure that we can find a way to make it work - this is basically the same circuit with a few tweaks. Dave Great Dave, glad you are catching these. I’m slightly dyslexic I think, With your keen eye we will have the build in great shape. Today I got a little time to check a few things out on the S100 bus access RAM R/W problem Using it as a slave I find I cannot write to S-100 RAM (as well as not read, all FF’s). I know this, because I switch from Z80->68K write at 0H and switch back and check if RAM changed. It did not! No problem BTW what so ever with onboard RAM or the ROM monitor. I am using our 4MG Static RAM board which with other CPU’s can often get well above a 10MHz clock. Tried a number of other S-100 RAM boards, Godbout, Fulcrum etc. All failed EXCEPT one, a Godbout RAM 16 board. It worked as best I can tell fine. But hear is the rub, only for the first 4K! This same board with a 8086 shows (correctly 64K) with my monitor memory map. This is a very fast board. Godbout rated it also for > 10MHz, but it’s nothing special. Does unfortunately use a PAL. When I switch the 68K board form my small 10 slot Test S-100 box to my main system, the 2MG RAM board partially works. Bytes show up mainly as “P” (proms), there are a few “R’s” however. Certainly I don’t get all FF’s. Even more mysterious the whole thing is largely independent of CPU clock speed. Tried 12 to 4MHz. All tests above, were at 4MKHz. It sounds like there is a very tight timing glitch. I just noticed the address lines are not latched on this board (U27, U28 & U32). Next chance I get I will search around for a signal to latch them Anyway wanted to save you discovering some or the above. Will be interested to see how you make out. John From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of yoda Oops - I mean you had J15 not K15 and it should be J14 (so many jumpers it is easy to make typos) Hi John 2 more corrections for the documentation. Under adding the EPROM/RAM circuitry - you say jumper K15 1-3 and 2-3 should be J14 1-3 and 3-4 both jumpers are vertical. Two paragraphs down you say bend back pin 6 of U34 from beginning of build - that should be U31 pin 9. I did not see any other errors so far. I am at the point of plugging in the RAM and eeproms. I will wait till tomorrow to do that test and starting looking at the S100 RAM (Did not get to spend as much time tonight as I had wanted). My monitor is currently burned with SP in S100 memory so I need to re-assemble the code with SP in the onboard RAM area - won't take long but need to do it and my stuff is currently in 28C64s so I need to swap in the 28C256's Yes all correct Dave, thanks John John Monahan Ph.D e-mail: mon...@vitasoft.org Text: mon...@txt.att.net From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of yoda Hi John Been working through your notes and found a couple errors I think. I have free running working great I am working through the DTACK and WAIT state circuit - 3rd paragraph where you are looking at signals on U40 (BTW I only have 74ls367 and it seems to work so far) I think you mean 7 is high and 9,11 and 13 will pules (not 79) but for this to happen I think you need to have U42 in plugged in as well. You do have it plugged in on your picture but don't mention to add it. If you don't then pin 7 will pulse. Further down though I am not there you on the Watchdog time in first paragraph you say insert JP9 that should be J9 instead. I am probably going to call it a night soon but it looks like things are working so far. Dave
Hi John - read through what you have updated so far looks good and I will be starting now. BTW you probably should update your web site to say V3 instead of V2 as on Andrew's site it is referred to as V3 and technically it is the third version if you count the Wilcox board as V1. Dave John. Thanks for the explanations - they make sense. Might want to publish what you have - more eyes could be helpful. I am ready to start populating - want to do some voltage checks, and clock - then will start populating enough to do the NOP tests - then I next plan to do the Character out loop with no memory to get that working then populate the memory and use the memory checking code that does not use a stack (all inline code) to make sure the on board ram is working then start branching out to check off board memory. I assume those are similar to the steps you have done. Dave Dave I am in the middle of bringing my board up. I have so far step by step assembly notes for everybody with tests at each step. I am bringing it up as a bus master first. Have monitor and onboard RAM working fine but for some reason all bus RAM is showing up as FF’s. Currently debugging! There are a lot of jumpers each of which will require a detailed explanation. I’m am trying to get it debugged/ written up before others start into it so excuse the quick reply. All the K’s have to do with master/slave switching. For a simple master, XFERI & XFERII just go to ground, K4 2-3 (slight bug, to have 68K LED active bend out pin 1 of U71 and wire wrap 1,2 & 3 together). JP13 is a carryover from the original Wilcox board and is basically now just a connection point in case one wants to hookup a external single step circuit as he had originally. Yes always closed. See below for others John From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of yoda Hi John I have some questions on the jumpers. I am not quite sure what the settings should be for K1, K2, and K4 as they are new and probably have something to do with the TMA stuff. Also it seems that JP13 must always be Closed or I don't understand the function of it. Here is what I have come up with so far - I am going to start using as a bus master with no SMB currently in the system I have labeled some with ? Could you clarify or confirm them? Thanks Dave J9 Open Watch Dog Timer ------- Closed J10 Closed Auto Vector enabled J13 Open Enable Various Interrupts J14 1-3, 2-4 ROM at XX8000 J15 Closed Enable Boot Feature JB1 1-2, 3-4 Values for 28C256 eeprom JB2 3-4, 7-8 Values for 62256 memory JP1 Open OV_A JP2 Open OV_B JP3 Open OV_C Do not add this circuit until later, it’s for DMA in slave mode will explain later. JP4 1-2 Connect to SDSB* JP5 Open S100 pin 65 Only if these signals are not generated by front panel or our SMB JP6 1-2 Bus_RESET* JP7 1-2 HOLD* JP8 1-2 SLAVE_CLR* JP9 1-2 POC* JP10 1-2 BUS_RESET* JP11 1-2 MWRT* JP12 1-2 Clock* JP13 1-2 ???? seems this needs to be always connected see above Do not add this circuit until later it’s for DMA in slave mode will explain later. JP14 Open BR* ??????? JP15 1-2 PHLDA* JP16 Open S100 pin 66 These are fine K1 1-3 XFERI ????? K2 3-4 XFERII ????? K3 1-2 NMI* K4 2-3 XFERII K5 2-3 DODSB* K6 2-3 HALT K7 2-3 bA20 ------- 1-2 P2 dependent Sets number of Wait States The whole U2,U3 cascade is for handshaking on master to slave transition and DMA designation In master mode this whole circuit can be ignored P5 1-2 TMAXPU* ????? P6 1-2, 5-6 Passes Master Reset through ???? For master P6 1-3 and 5-6 check pins carefully -- -- -- |