took another look at this V2 SMB, U33, the 74LS175 is clock
triggered on the rising edge. The signal coming from U31B
(pin 6) may be arriving too late and somehow the data bus
has lost it by the time it rises into U33. I’m seriously
considering doing a V3 SMB using a few GAL’s and more
functionality, since I don’t have your problem could you
check if this is the problem.
will invert the signal coming from U31 pin 6, so the start
of the rising pulse will latch the data lines into U33.
Fortunately the is a spare gate on the board U10B, a
74LS00. Jumper its pin 4 to Vcc. Bend out pin 6 of U31B.
Jumper this pin to pin 5 of U10. Jumper U10 pin 6 to pin 9
of U33. Then see if you can get home with the 80386.