Good point Curt, and definitely not a whine. I had not really looked at the F520’s before. To some extent you are comparing apples to oranges. For P=Q on the LS682’s the typical delay is 13 ns, max 25 ns (TI datasheet). For P=Q for the F520 its 5 and 5.5. However that’s a 74Fxx part, I cannot find a corresponding LS520 datasheet. The delay is more a function of the 74LS/74F part rather than the internal chip layout. A brief look on the web did not turn up 74F682’s or 74ALS682’s. If they exist, I bet they would be comparable to the 520. Where are you getting your F520’s from BTW. Going forward, since I really use the LS682 pin 1 (used for P>Q), we could have a jumper to allow either chip on the board. John From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of curt mayer A lot of these designs want to be pushed a little for clock rate, and It feels really odd sticking a slow part like a 'ls682 in my critical address decode path, especially when it's cascaded like in the rom/ram board. sticking 35 ns memory in there and then blowing another 30 ns just to decode the address lines to get a chip select will keep you from running at 10mhz without wait states. an 'F520 will do the same job in half the time, if you ground the unused p>q output; so all my '520s in '682 sockets have pin 1 lifted and wired to ground with a scrap of kynar. and my chip selects come out 10ns earlier. it this just a whine? I really dislike the '682, since you can't get any faster parts with this pinout that have the internal pullup. --curt, on a quest for a 12mhz s100 0WS z80. -- |