S100 Computers -Z80 V3 CPU Board

An S-100 Bus Z80 V3 CPU Board.

Introduction
Our original S100 Bus Master Z80 CPU board came out in 2010. It has shown itself the be a stable and very reliable CPU board.
Most systems handle a clock frequency of 8MHz (with 3 IO wait states). By switching out some 74LSxx chips to 74Fxx chips the board runs in three terminated S100 bus I here have easily and reliably at 10MHz.
The circuit used was almost an exact copy of the Intersystem's Z80-II CPU board.

Apart from all the then common features found on a Z80 board (and being completely S-100 IEEE-696 compliant), it had an extremely clever and powerful ability to allow the Z80 to address up to 1 MG of RAM in two 16K "windows" within the Z80's address space.
This is described elsewhere and will be discussed in more detail below.
But its primary importance is that it could be used to address greater than 64K of RAM for CPM3 and that it can be used to load/examine 8086 code at the top of the 1MG RAM/ROM address space.

Even with the above windowing feature there was quite a bit of spare space on the board.
I decided to enlarge the boards features. This new V3 Z80 Master Z80 CPU board has the following features.

1.    Two 16K RAM/ROM addressable windows which can reside anywhere in the first 1MB of the S100 Bus Address space
2.    Switch selectable ability to add 0-8 CPU wait states to Memory, IO or INTA CPU cycles.
3.    An IOBYTE 8 bit switch selectable IO port for flexible monitor options.
4.    A USB port to up/download code to/from a PC.
5.    This USB port can also be configured to act as a Console IO port for the Monitor/CPM etc. instead of the Propeller Console IO board.
6.    A reliable S100 bus Reset, POC and Slave Clear circuit for systems/motherboards that do not provide these signals.
7.    The ability to activate each of the S100 bus TMA0,1,2,3 lines for Master/Slave CPU control of the bus.
8.    An "IMSAI" style 8 pin ribbon cable connector to hook up to a front panel board.
9.    The board will work with all S100 computers hardware and software as the previous Z80 CPU boards.

With almost any RAM board and Disk Controller board you should have a basic working S100 bus system.

That's the good news, the bad news is this board is now quite complex. Its a densely packed 4 layer board where 70% of the board needs to be built/working before anything works.
It's probably not suitable for a beginner S100 bus board builder.

The Z80 CPU Board Circuitry
The complete schematic of the board can be seen here. At first it does look a bit scary, but once you split it into its components it gets a lot easier. First the board circuit can be split into 3 parts. First the address/data line components, second the S-100 status and control signals and third the "new" USB port, IOBYTE port and TMA selection lines. The first two are almost identical to that on the V1 and V2 boards. Let us first look at the address lines.

Address lines.
Pushing the sixteen Z80 address lines out on to the S-100 bus on Z80 boards is usually not complicated. Typically it is done with a two buffer/driver IC's (that can be tri-stated by the S-100 ADSB* signal if the board is no longer the bus master).   The reason this board is more complicated is that we have added the capability to intercept the address the Z80 "thinks" it is putting out with another actual address on the bus. The circuitry itself is a bit complicated, but for most it can be regarded as a "black box" that has the following properties:-

There are two address space windows 0-3FFFH and 4000H to 7FFFH that intercept the Z80 address lines and modify them depending on 8 bit "offset values' placed in ports at D2H and D3H on the board (U17 & U16).

The window "offset value" placed in port D2H (or D3H) is used as the top six bits of a 20-bit address space (allowing up to 1MG to be addressed).

Upon board reset, these "offsets" are 0H, so the address put out by the Z80 is the same as that which appears on the bus.

This address modification does not affect Z80 addresses above 7FFFH.

The two 16K windows are actually independent of each other and while often contiguous, can be different and used to move data from one memory location to another anywhere in the 1MG address space.

I know the above sounds confusing. Lets take an example. Suppose you want to see what is in RAM at FC000H to FFFFFH (a region addressed by say a 8086 CPU reset/monitor). If you output to port D2H the "offset value" 0FCH and then examine with your Z80 monitor program memory from 0H to 3FFFH what the Z80 will actually get is what is in RAM at FC000H to FFFFFH. If you have no RAM at that location in your system you will just see FFH's. Until you issue a new value to port D2H any Z80 code addressing memory from 0 to 3FFFH will actually be looking in hardware at RAM at FC000H to FFFFFH. If you placed 80H in port D2H you would be looking at a 16K window starting at 80000H in RAM. If you issue 0H to port D2H (or do a hardware reset) the Z80 address lines match with the hardware address lines (i.e. a 16K window starting at 0H in RAM -- or no actual translation).

The second port (D3H) works exactly the same except its window is 4000H to 7FFFH. So again if you issued 0FCH to port D3H When the Z80 accesses memory between 4000H to 7FFFH it will actually get in hardware memory at FC000H to FFFFFH.
Note the port address (D2H & D3H) are configured using jumper P2 with only 5-6 connected. (1101 + U27A)
You can assign another port number if you like with jumpers on P2 (0xH -Fxh).

Here is a picture of the address translation circuitry.

The relevance for all this becomes very apparent if you want to use CPM3 (or CPM+). See here for a more detailed description of that operating system.
By utilizing the above 16K windows you can very quickly and easily implement a banked CPM3 system.
However we are getting ahead of ourselves. Remember for now, upon startup/reset, the Z80 sees only 64K of RAM just like any other S-100 CPU board.

The EPROM/Power On Jump Circuit.
The Z80 boots up on reset at 0H in RAM. Typically we want it to jump to high RAM (e.g. E000H or F000H) where we have a Monitor program in EPROM.
For this we need to force to start at that location upon power on or reset. The circuit below accomplishes this.

The trick is to force 00H (NOP's) on to the data bus until the desired Address is reached. The Boot (upper 4) address lines are set with a jumper (P3) of U15. In my case I use F000H. So upon reset, all address lines are 0H. The output from U29 will turn on the inputs from U18. These will set the data lines to 0H. The Z80 will this see only the NOP opcode on its data lines. This will increase the address lines one byte. The process will repeat until the U15 matches the address lines (A12-A15) with that on Jumper P3. At that point pin 19 of U15 will go low. ROM_SELECT* will go low. This causes U29 to switch off U18 and turn on the EPROM outputs.

Note, Pin 1 & 19 of U20 the "Normal" buffer to input data from the S-100 bus to the Z80 will be high all this time because the READ_STROBE input never goes high.   It is inhibited by the "Jump Enable" output of U29 going (via pin #3 of U41) to the Boards main READ_STROBE/pDBIN signal. The latter is not shown in the above diagram but can be seen in the main schematic.

Here is a Logic Analyzer Display of some of the signals (using a USBee SX).

You can place the EPROM on any 4K boundary in the Z80's 64K address space.
I use 0F000H to 0FFFFH for the following Master ROM Monitor. This monitor code can be downloaded from the bottom of this page.
I like to use Atmel AT28C64B EEPROMS and a Wellon VP-290 (or later) Programmer.

Wait State Generator Circuits
Since we will be pushing this board to speeds uo to 10MHz we will need to have the ability to add bus wait states for use with older slower S-100 boards.
The usual tried and true 74LS165 circuit is used. Here is an example:-

By setting the switch anything from 0 to 8 wait states can be added to bus signals. On this board I have 2 wait state generators to allow one to individually tune wait states for the onboard ROM, M1 type Memory accesses or any memory access and I/O port access. For the Z80 an M1 type memory access has the shortest access time, so with a slow RAM board you can first try setting a M1 access wait state addition, if that does not work you can fall back to (slower) all memory accesses. With all the current S100 Computers Memory boards normally none, 1 or 2 M1 wait states is all that is required.

Status Signal Decoding.
The control signals from the Z80 cannot be directly used on the S-100 bus. They must be first converted into what is essentially Intel 8080 type signals. The circuitry for this is a bit complex and is shown here just for completeness. There are a number of Jumper options to alter the S100 bus signals. These are described in detail for the V2 board Z80 circuit and summarized in a table below. For detail, see the above complete schematic .pdf file.

Z80 Control Circuit

Power Up, Reset Circuit.
Most S100 Bus motherboards provide a negative going pulse to the S100 Bus Reset line (75), Slave Clear (54) and Power On (99) lines on startup.
Alternatively the signals are provided by the Front Panel if the system has one.
However some setups assume the Master CPU will provide these signals.
Previous S100 Computers boards provided a Transistor/Capacitor discharge circuit which did not work very good.
Here we will use an Analogue Devices DS 1233-5 to generate the signals. Here is the circuit:-

One minor change to the original V2 Z80 Board circuit is the CPU data lines are now each pulled up with a 4.7K resistor (RR10) located under the Z80 CPU.
You need to get a 40 pin socket of the type that has a small bridge across the clear are in the middle of the socket.
Cut out this bridge leaving a socket with a large clear central area.
This 4.7K resistor network on the Z80 data lines is required for a Front Panel connection.

The V3 Board Circuit Additions.
The USB Port
The USB connection uses the same DLP-USB1232H Parallel Port to USB module we used on our Serial IO Board.
This module while not inexpensive is very simple to interface and is very reliable. There are a few types. Make sure you use this exact one.
Here is the circuit.

There is one data input port to the Z80 data bus, One status input port to the Z80 data bus and one output data port from the Z80 data bus. The default status port is E8H and the data port is E9H.
These designations can be changed with jumpers on P13 (E8H-EFH)
The updated Z80 ROM "Master.z80" monitor (Version V6.2 and greater) has been updated to send and receive data with the "X" command (see below).

A very important jumper is K9. If jumpered 1-2 The Z80 monitor will act as it always did in the past using the Propeller Console IO port for all Console IO.
If K8 is jumpered 2-3 Then the Z80 monitor communicates over the USB port and is expecting a USB linked terminal at the other end. This is typically a PC program like Tera Term etc.

The IOBYTE Port
The second addition is an "IOBYTE" data input port. Normally with the S100 Computers Boards this 8 bit Monitor IO configuration ports resides on the SMB at Port EFH. The Dip switch SW1 allows the IOBYTE bits to be changed. By moving the SMB IOBYTE port on to this Master Z80 board, the SMB is not required for most software. However if the SMB is in the system (to display the address lines, data and bus status lines etc.) you must inactivate the IOBYTE port on this Z80 CPU board by removing the Jumper 15-16 on P19. Otherwise you will have two boards providing possibly conflicting IOBYTE values. Here is a picture of the circuit.

The DMA Selection Circuit
The third addition is the circuit to activate one of the S100 Bus TMA lines.
These lines are used to activate one of the many S100 Computers Slave CPU's.

The circuit is quite simple. Again we use a Jumper on P19 to activate a 4 bit output port (U59) on this board
When activated (and the slave CPU is now in control) one of the 4 LEDs (D2,D3,D4 and D7) also lights up.
The TMA line is activated by outputting to port EFH 1, 2, 4 or 8. Here is a picture of the circuit:

Finally this board brings the internal Z80 Data lines out to a 16 DIP connector at the top RHS of the board for possible connection to an IMSAI like front panel.

The Onboard ROM
The Z80 Master monitor has by now evolved into a sophisticated monitor with many menu options. It no longer fits into the F000H-FFFFH address space.
Rather than drop the monitor down to E000H-FFFFH we leave it at F000H-FFFFH and use hardware on the board to "page in" either the lower half of an 8K ROM or the upper half of the same ROM.
This is all explained here in detail in the monitor software section of this site. I use an EEPROM such as a Samsung MK28C64A 8KX8 EEROM.

Remember BTW, you can totally inactivate the ROM. (That is a very important function for CPM3).
You do this by outputting xxxxxxx1 to port D3H. You can shadow it back in by xxxxxxx0 to port D3H. i.e. bit 0 of port D3H.

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